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A heuristic for test scheduling at system level

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3 Author(s)
Flottes, M.-L. ; LIRMM, Univ. of Montpellier, France ; Pouget, J. ; Rouzeyre, B.

Summary form only given. This paper considers the test-scheduling problem of a SoC. The proposed approach is based on a "sessionless" test scheme. It minimizes the system test time while respecting a power dissipation limit and test resource sharing constraints. Experimental results show that our approach outperforms other related test scheduling solutions

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Date of Conference:

2002