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High-level modeling and design of asynchronous arbiters for on-chip communication systems

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4 Author(s)
J. -B. Rigaud ; TIMA Lab., Grenoble, France ; J. Quartana ; L. Fesquet ; M. Renaudin

Summary form only given. This work presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied from the perspective of making easier and more practical the design of future GALS or GALA SoCs. This work focuses on high-level modeling and delay-insensitive implementations of low-power and reliable fixed and dynamic priority arbiters

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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