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Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications

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7 Author(s)
Sassatelli, G. ; LIRMM, Montpellier, France ; Torres, L. ; Benoit, P. ; Gil, T.
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New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures

Published in:
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Date of Conference: 2002

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