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Hardware-assisted data compression for energy minimization in systems with embedded processors

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4 Author(s)
Benini, L. ; Bologna Univ., Italy ; Bruni, D. ; Macii, A. ; Macii, E.

In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and efficient architecture for on-the-fly data compression and decompression whose field of operation is the cache-to-memory path. Uncompressed cache lines are compressed before they are written back to main memory, and decompressed when cache refills take place. We explore two classes of compression methods, profile-driven and differential, since they are characterized by compact HW implementations, and we compare their performance to those provided by some state-of-the-art compression methods (e.g., we have considered a few variants of the Lempel-Ziv encoder). We present experimental results about memory traffic and energy consumption in the cache-to-memory path of a core-based system running standard benchmark programs. The achieved average energy savings range from 4.2% to 35.2%, depending on the selected compression algorithm

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Date of Conference:

2002