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An efficient compiler technique for code size reduction using reduced bit-width ISAs

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5 Author(s)
Halambi, A. ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Shrivastava, A. ; Biswas, P. ; Dutt, N.
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For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space-efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This future, however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the function-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage: of both Instruction Sets. We also demonstrate improved code size reduction, for the MIPS 32/16 bit ISA, using our technique. Our approach more than doubles the code size reduction achieved by existing compilers

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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