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Gate level fault diagnosis in scan-based BIST

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2 Author(s)
Bayraktaroglu, I. ; Comput. Sci. & Eng. Dept., California Univ., La Jolla, CA, USA ; Orailoglu, A.

A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test vector information and enables location identification of single stuck-at faults to a neighborhood of a few gates through set operations on small pass/fail dictionaries. The proposed scheme is applicable to multiple stuck-at faults and bridging faults as well. The practical applicability of the suggested ideas is confirmed through numerous experimental runs on all three fault models

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Date of Conference:

2002

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