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Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification

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4 Author(s)
M. J. Ciesielski ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; P. Kalla ; Zhihong Zheng ; B. Rouzeyre

This paper presents a new, compact, canonical graph-based representation, called Taylor expansion diagrams (TEDs). It is based on a general non-binary decomposition principle using Taylor series expansion. It can be exploited to facilitate the verification of high-level (RTL) design descriptions. We present the theory behind TEDs, comment upon its canonicity property and demonstrate that the representation has linear space complexity. Its application to equivalence checking of high-level design descriptions is discussed

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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