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A cell transistor scalable DRAM array architecture

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2 Author(s)
Takashima, D. ; Memory LSI Res. & Dev. Center, Toshiba Corp., Yokohama, Japan ; Nakano, H.

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 5 )