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In this paper, a high speed and low power adder is designed using a new logic-design style called Pseudo Dynamic Logic (SDL). Traditional dynamic logic is pre-charged to a default value and in the evaluation phase is changed to its real logic, However, in this new logic style, the internal nodes are charged to an intermediate pre-charge value, so that the evaluation is performed faster. A 32-bit CLA adder has been designed and simulated using HSPICE Level 49 parameters of a 0.6 μm CMOS process. Simulated measurements on this adder show that the worst-case delay is 1.56 ns. This shows 2.1 times speed improvement and 21.2% area saving in comparison to a domino dynamic logic design implemented with the same technology.