By Topic

Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Cho, G.R. ; Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA ; Chen, T.

We present a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method based on a genetic search. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/CMOS logic gates using BDDs. The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay or power consumption or both in a 0.25 μm CMOS process. The average area, power consumption, and power-delay product of ISCAS85 and MCNC91 benchmark circuits using the proposed method are 25%, 40%, and 45% better than their static counterparts, respectively.

Published in:

Quality Electronic Design, 2002. Proceedings. International Symposium on

Date of Conference:

2002