By Topic

Device physics impact on low leakage, high speed DSP design techniques

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Scott, D. ; Texas Instruments Inc., TX, USA ; Shaoping Tang ; Song Zhao ; Nandakumar, M.

The limitations of implementing low leakage schemes and their application to current state of the art components is discussed In addition to source subthreshold leakage, both gate induced diode leakage current and tunneling gate leakage current must be comprehended A viable leakage reduction strategy requires extensive modeling of circuits in the standby mode as well as new demands on the understanding of transistor physics. The ramifications of the physics of the behavior of transistors under conditions of high electric fields apply not only at the circuit level but can also impact the chip level system. In the coming applications of mobile electronics, understanding of this concept is critical.

Published in:

Quality Electronic Design, 2002. Proceedings. International Symposium on

Date of Conference:

2002