By Topic

Design of ESD protection device using statistical methods

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shigyo, N. ; Syst. LSI Design Div., Toshiba Corp., Japan ; Kawashima, H. ; Yasuda, S.

This paper describes an ESD protection device design to minimize its area Ap while maintaining the breakdown voltage VESD. Hypothesis tests were performed to find the applied surge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate VESD. An optimum device structure, where a salicide block was employed, was found using statistical methods and TCAD.

Published in:

Quality Electronic Design, 2002. Proceedings. International Symposium on

Date of Conference: