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Design of ESD protection device using statistical methods

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3 Author(s)
Shigyo, N. ; Syst. LSI Design Div., Toshiba Corp., Japan ; Kawashima, H. ; Yasuda, S.

This paper describes an ESD protection device design to minimize its area Ap while maintaining the breakdown voltage VESD. Hypothesis tests were performed to find the applied surge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate VESD. An optimum device structure, where a salicide block was employed, was found using statistical methods and TCAD.

Published in:

Quality Electronic Design, 2002. Proceedings. International Symposium on

Date of Conference:

2002

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