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ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process

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4 Author(s)
Ming-Dou Ker ; Integrated Circuits & Syst. Lab., Nat. Chiao-Tung Univ., Taiwan ; Chien-Hui Chuang ; Kuo-Chun Hsu ; Wen-Yu Lo

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique, can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-μm salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ∼65% by this substrate-triggered design.

Published in:

Quality Electronic Design, 2002. Proceedings. International Symposium on

Date of Conference: