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Synthesis of selectively clocked skewed logic circuits

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4 Author(s)
Aiqun Cao ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; N. Sirisantana ; Cheng-Kok Koh ; K. Roy

Skewed logic circuits with a selective clocking scheme have performance comparable to that of Domino logic, but consume much lower power. Unlike Domino, the reconvergent path problem in skewed logic circuits may be overcome without logic duplication due to the static nature of skewed logic. In this paper, we propose a novel approach that alleviates the need for logic duplication when dealing with reconvergent paths in skewed logic circuits. We also propose a dynamic programming-based heuristic to determine a low-power clocking scheme for skewed logic circuits. Experimental results show that 32% of gates in a skewed logic circuit are duplicated, whereas 69% of gates in a Domino logic circuit are duplicated. The total power saving of skewed logic over Domino logic is 32.6% on average.

Published in:

Quality Electronic Design, 2002. Proceedings. International Symposium on

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