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Design of an image edge detection filter using the Sobel operator

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3 Author(s)
Kanopoulos, N. ; Research Triangle Inst., Research Triangle Park, NC, USA ; Vasanthavada, N. ; Baker, R.L.

The architecture of the edge detector presented is highly pipeline to perform the computations of gradient magnitude and direction for the output image samples. The chip design is based on a 2-μm, double-metal, CMOS technology and was implemented using a silicon compiler system in less than 2 man-months. It is designed to operate with a 10-MHz two-phase clock, and it performs approximately 200×106 additions/s to provide the required magnitude and direction outputs every clock cycle. The function of the chip has been demonstrated with a prototype system that is performing image edge detection in real time

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 2 )

Date of Publication:

Apr 1988

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