Cart (Loading....) | Create Account
Close category search window
 

Effects of device design on InP-based HBT thermal resistance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Thomas, S., III ; Hughes Res. Labs., Malibu, CA, USA ; Foschaar, J.A. ; Fields, C.H. ; Madhav, M.M.
more authors

The thermal resistance of InP-based single and double heterojunction bipolar transistors has been measured. The double heterojunction bipolar transistor (DHBT) device employs an InP collector to improve thermal conductivity and reduce the base-emitter junction temperature rise. DHBTs were grown with heavily doped InGaAs or InP sub-collectors for low resistance contacts. As expected, the all-InP collector (sub-collector and collector) had the lowest thermal resistance while the all-InGaAs collector (sub-collector and collector) had the highest thermal resistance. For a device with emitter size of 1 × 3 μm2, the room temperature thermal resistance of the all-InP collector DHBT was 3.9°C/mW. The DHBT with an InGaAs sub-collector had a thermal resistance of 5.6°C/mW, while the SHBT had a thermal resistance of 12.3°C/mW. Also compared were effects of device layout parameters on thermal resistance and the effect of the topside metal thickness. Devices with the largest perimeter-to-area ratio had the lowest thermal resistance when normalized to emitter area. HBTs with conservative alignment tolerances (L1) had similar thermal resistance to those with aggressive alignment tolerances (L2). The reduced parasitic capacitance of the L2-style SHBT improved the device f T from 150 to 183 GHz at 6.0-mA collector current. Alternately, the reduced parasitics allowed the SHBT to operate at 150 GHz fT at 2.9 mA, reducing the junction temperature rise by more than half. Doubling the topside metal thickness improved the thermal resistance by 31% at room temperature

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:1 ,  Issue: 4 )

Date of Publication:

Dec 2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.