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Accurate delay estimation model for lumped CMOS logic gates

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2 Author(s)
Vernuru, S.R. ; Dept. of Electr. Eng., Toledo Univ., OH ; Smith, E.D.

Recently a novel slope delay model for timing verification in digital CMOS circuits has been presented by H.G. Yang and D.M. Holburn (see ibid vol.137, p.405-12, 1990). Three different classifications were made, based on the risetime (slope) of the input waveforms, as follows: quick-no effect of input risetime on the output voltage; intermediate-small effect of input risetime on the output delays; and slow-significant effect of input risetime on the output delays. In the analysis of the slow waveform, the input voltage to the inverter was taken as 0.5 (Vdd-Vtn+kt0 ), because otherwise there is no analytic solution. This assumption is valid as long as the input voltage is rising. If this approximation is continued after the input voltage reaches V dd, then the current through the NMOS transistor is consistently underestimated, and the fall-time is overestimated. Hence, a more accurate representation of input waveform is necessary to obtain more reliable delay estimates

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:138 ,  Issue: 5 )