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Path delay fault test generation for standard scan designs using state tuples

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3 Author(s)
Yun Shao ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Pomeranz, I. ; Reddy, S.M.

In this work we propose a novel concept called state tuple to represent the states of lines in a circuit for the generation of two pattern tests. The proposed approach is described in detail for generating robust two pattern tests for path delay faults in standard scan designs. Using the proposed approach we also report experimental results of a test generator for robust path delay faults in standard scan designs. The results show that the test generator achieves high efficiency with reduced implementation complexity

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Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.

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