A partitioning and storage based built-in test pattern generation method for scan circuits

We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.