Reformatting test patterns for testing embedded core based system using test access mechanism (TAM) switch [SoC]

In this paper, a new algorithm for reformatting the test vector of system on chip (SOC) with test access mechanism (TAM) has been proposed. Exhaustive experimentation has been conducted by employing random reformatted test vectors for a variety of SOCs, constructed with the ISCAS sequential benchmark circuits. For a limited number of input pins, which have been provided for testing the SOC, the proposed algorithm drastically reduces the test-time as well as the hardware.