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On the design of low-voltage, low-power CMOS analog multipliers for RF applications

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3 Author(s)
Debono, C.J. ; Dipt. di Elettronica, Pavia Univ., Italy ; Maloberti, F. ; Micallef, J.

Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz application. Measurement results of the prototypes are comparable to other higher voltage designs.

Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 2 )

Date of Publication: April 2002

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