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Power-optimal encoding for a DRAM address bus

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2 Author(s)
Wei-Chung Cheng ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; M. Pedram

This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we present a power-optimal encoding, named Pyramid code. Extensions of the basic code address different types of DRAM devices. The proposed codes reduce power dissipation on the memory bus by a factor of two or more.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 2 )