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Analysis of dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for on-chip cache

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8 Author(s)
F. Hamzaoglu ; Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA ; Y. Ye ; A. Keshavarzi ; K. Zhang
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This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 2 )