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A heuristic for clock selection in high-level synthesis

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4 Author(s)
Ramanujam, J. ; Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA ; Deshpande, S. ; Jinpyo Hong ; Kandemir, M.

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal

Published in:

Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.

Date of Conference:

2002

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