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Implementation of space-time equalizer using multiple single-constrained SMI array processors and MLSE

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2 Author(s)
M. Fujii ; Mobile Terminal Lab., Fujitsu Labs., Ltd, Yokosuka, Japan ; T. Toda

We implemented a space-time equalizer using two sets of single-constrained sample matrix inversion array processors and a maximum-likelihood sequence estimator by using digital signal processors and field-programmable gate arrays. One of the array processors constrains the direct path, sends the one-symbol-delayed path component to the array output, and suppresses the paths with longer delays. The other array processor constrains the one-symbol-delayed path, sends the direct path component to the array output, and also suppresses the paths with longer delays. The desired paths, thus, extracted, whose signal-to-interference-plus-noise-ratios are improved in both path-diversity branches, are then combined by using a branch-metric-combining Viterbi equalizer. We implemented a receiver equipped with this equalizer and evaluated its bit-error rate performance by using a channel emulator. Experimental results indicate that the space-time equalizer provides both space diversity gains and path diversity gains while suppressing signals on paths with long delays

Published in:

IEEE Transactions on Wireless Communications  (Volume:1 ,  Issue: 2 )