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A synthesisable VHDL model for an easily testable generalised multiplier

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3 Author(s)
Aziz, S.M. ; Sch. of Electr. & Inf. Eng, Univ. of South Australia, Mawson Lakes, SA, Australia ; Basheer, C.N. ; Kamruzzaman, J.

This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two's complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for, automatic generation of vectors of variable lengths

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Date of Conference:

2002