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A flexible embedded SRAM compiler

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3 Author(s)
Yong Liu ; Inst. of Microelectron., Tsinghua Univ., Beijing, China ; Zhiqiang Gao ; Xiangqing He

SRAM compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper, a high-speed embedded SRAM compiler is described. It is based on TSMC's 0.5 μm CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k×64=1 Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM compiler can be easily integrated into Cadence and other CAD frameworks

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Date of Conference:

2002

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