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Generating small test sets for test compression/decompression scheme using statistical coding

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2 Author(s)
Ichihara, H. ; Fac. of Inf. Sci., Hiroshima City Univ., Japan ; Inoue, T.

A test compression/decompression scheme using statistical coding is proposed for design-for-testability (DFT) in order to reduce test application cost. In this scheme, a given test set of a VLSI circuit is compressed by statistical coding beforehand, and then decompressed while the VLSI circuit is tested. Previously, we proposed a method for generating test sets suitable for the test compression scheme. The method generates a small compressed test set, although the number of test-patterns included in the test set is not always small. In this paper, we propose a method to generate highly compressible test sets while keeping the number of generated test sets small. Experimental results show that our method can generate small, compressible test sets in short computational time

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Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

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