By Topic

Generating small test sets for test compression/decompression scheme using statistical coding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ichihara, H. ; Fac. of Inf. Sci., Hiroshima City Univ., Japan ; Inoue, T.

A test compression/decompression scheme using statistical coding is proposed for design-for-testability (DFT) in order to reduce test application cost. In this scheme, a given test set of a VLSI circuit is compressed by statistical coding beforehand, and then decompressed while the VLSI circuit is tested. Previously, we proposed a method for generating test sets suitable for the test compression scheme. The method generates a small compressed test set, although the number of test-patterns included in the test set is not always small. In this paper, we propose a method to generate highly compressible test sets while keeping the number of generated test sets small. Experimental results show that our method can generate small, compressible test sets in short computational time

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Date of Conference:

2002