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A comprehensive fault model for deep submicron digital circuits

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3 Author(s)
Abraham, J.A. ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; Krishnamachary, A. ; Tupuri, R.S.

Identifies the broad categories of defects which need to be considered in DSM technologies. We show that many of these defects cannot be detected using existing fault models and test approaches, and propose a new fault model for DSM circuits which incorporates logic levels as well as path delay information to deal with both functionality and performance. We show that tests derived using this model can be used to effectively screen chips for defects which affect the functionality and performance of the chips, and that the approach reduces the test costs and defect levels when compared with conventional approaches. Experimental results on large benchmark circuits are used to demonstrate the usefulness of the approach

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Date of Conference:

2002