We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

A fault-tolerant FPGA-based multi-stage interconnection network for space applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Alderighi, M. ; Ist. di Fisica Cosmica "G. Occhialini", CNR, Milan, Italy ; Casini, F. ; D'Angelo, S. ; Salvi, D.
more authors

Current space applications are pushing for improved on-board processing abilities, in terms of higher computing power, flexibility and fault-resistance, in order to keep up with the huge amount of collected scientific data. Multiprocessor systems seem a viable solution to match these requisites. In particular, systems employing multistage interconnection networks (MINs) offer the advantage of an effective resource allocation, depending on variable workloads and occurrence of faults. The paper presents a fault-tolerant interconnection mechanism, based on redundant MIN, for multi-sensor systems. The proposed system is implemented by means of field programmable gate arrays (FPGAs) and allows a flexible re-organization of computing resources in dependence of varying operating conditions. Fault-tolerance is achieved both by exploiting the MIN intrinsic redundancy and by using an efficient FPGA reconfiguration technique

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Date of Conference: