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Testing the unidimensional interconnect architecture of symmetrical SRAM-based FPGA

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4 Author(s)
Renovell, M. ; LIRMM-UM2, Montpellier, France ; Faure, P. ; Prinetto, P. ; Zorian, Y.

This paper proposes a new and original solution to test the unidimensional interconnect architecture of a RAM based FPGA by exploring the specific properties of these blocks. The method to find a reduced set of configurations is proposed and the sequence of test vectors required for each configuration is given

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Date of Conference:

2002

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