Signal margin analysis for DRAM sense amplifiers

The sense amplifier (SA) design and the bit line architecture determine the minimum detectable signal limit for a dynamic random access memory (DRAM) cell readout operation. Increasing memory sizes, smaller feature sizes and lower operating voltages make it more important to understand the cell signal sensing operation, the signal of memory cells and the limiting factors. This paper presents a measurement method to evaluate the signal created by the memory cell and the sense amplifier uniformity at product level. Measurements of the sense amplifier offset distribution and sense amplifier signals for 0's and 1's for all memory cells will be presented. Spatial analysis gives further insight into the sensing limitations. This can be used to improve the circuit modeling of the sense amplifier and to simulate process variations. The results for a 64Mbit 0.19 μm memory device will be shown, having a sense amplifier imbalance