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A novel CAM/RAM based buffer manager for next generation IP routers

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3 Author(s)
Chie Dou ; Nat. Yunlin Univ. of Sci. & Technol., China ; Shing-Jeh Jiang ; Kuo-Cheng Leu

This paper proposes an integrated CAM/RAM based buffer manager for next-generation IP routers. Buffer allocation. is accomplished by inspecting the length field in the IP header of an incoming packet, the wasted buffer area is optimized, and the hardware implementation is simple. The data buffer is configured according to the cumulative packet size distribution observed from the underlying network thus increasing the efficiency of the memory utilization. The buffer manager also supports the multicast management in an elaborate manner. In addition, it supports different-sized block movement of the packet data between the data buffer and the transmission media. Finally, it need not maintain the free buffer list; i.e., enormous and repeated 'insert' and 'delete' operations of pointers in a linked list are eliminated

Published in:

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

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