By Topic

Improving SMT performance scheduling processes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Goncalves, R. ; Departamento de Informatica, Univ. Estadual de Maringa, Brazil ; Navaux, P.

Nowadays, SMT (simultaneous multithreaded) architectures use aggressive techniques to execute instructions from different threads on shared resources simultaneously. SEMPRE (Superscalar architEcture with Multiple PRocesses in Execution) is a type of SMT architecture which was proposed to schedule and execute processes simultaneously. The waste of time on both process scheduling and context switching is minimal, providing high performance during the execution of applications. The SEMPRE architecture was analyzed and evaluated using execution-driven simulations of the SPEC benchmark suite. The simulations showed that process scheduling by hardware can provide reasonable performance over process scheduling by the operating system on equivalent SMT architectures, with little extra hardware. This higher performance is achieved because the hardware makes better use of the process time-slice. The performance of SEMPRE is always higher than the performance of traditional SMT, achieving more than 21% in some cases

Published in:

Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on

Date of Conference: