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Simultaneous cycle-time reduction and output enhancement in a fully loaded foundry wafer fab

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9 Author(s)
Ho, C.M. ; United Microelectron. Corp., Hsin-Chu, Taiwan ; Chen, T.C. ; Hseih, P. ; Chu, C.
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A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output increase of over 20%. In the mean time, the fab WIP level was reduced by more than 20% without any compromise in line-yield or customer delivery.

Published in:

Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on

Date of Conference:

2000