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Interpolation based direct digital frequency synthesis for wireless communications

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2 Author(s)
Eltawil, A.M. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Daneshrad, B.

In this paper, a compact architecture for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sine and cosine functions compared to existing architectures, with minimal hardware overhead. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). A DDFS with 64 dBc SFDR, 10-bit output resolution and 32 bit phase accumulator requires only 104 bits of ROM storage. The ROM size is consistently less than 1 Kbits for SFDR up to 85 dBc.

Published in:

Wireless Communications and Networking Conference, 2002. WCNC2002. 2002 IEEE  (Volume:1 )

Date of Conference:

17-21 Mar 2002