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A 0.6/spl mu/m double-poly CMOS 12b ADC uses a number of different techniques to obtain low power. The ADC achieves 68dB SNR at 21 MSample/s, consuming 30mW at 2.7V. Die area is 2.56mm/sup 2/.
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International (Volume:1 )
Date of Conference: 7-7 Feb. 2002