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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

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8 Author(s)

An efficient substrate-noise-reduction technique for synchronous CMOS circuits shows >2/spl times/ noise reduction with penalties of 3% area and 4% power increase in a 5k-gate synchronous CMOS circuit fabricated in a 0.35 /spl mu/m CMOS process on an epi-type substrate.

Published in:

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International  (Volume:1 )

Date of Conference:

7-7 Feb. 2002