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A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission

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6 Author(s)
Noguchi, H. ; Fiber Opt. Devices Div., NEC Corp., Kawasaki, Japan ; Tateyama, T. ; Okamoto, M. ; Uchida, H.
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A 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5 /spl mu/m SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2 mUIrms jitter generation and 0.45 UIpp jitter tolerance in a 4-80 MHz range. Power dissipation is 1.45 W from a 3.3 V supply.

Published in:

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International  (Volume:1 )

Date of Conference:

7-7 Feb. 2002