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A 3 V /spl Delta//spl Sigma/ receiver with sampling rate enhancement for CDMA baseband processor IC

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3 Author(s)
E. Liu ; LSI Logic Corp., Milpitas, CA, USA ; M. Chen ; M. Pan

A 3V /spl Delta//spl Sigma/ CDMA baseband receiver has been designed which has a 4th-order single-loop modulator that enhances the effective sampling rate without increasing the actual rate, achieves 62 dB DR (dynamic range), consumes 22 mW, and occupies 1.3 mm/sup 2/ in 0.25 /spl mu/m CMOS. This receiver is part of an 8 M transistor 10.5/spl times/10.5 mm chip which integrates receiver, transmitter, voice codec, 10 bit ADC and DAC, PLL, 32 kHz oscillator, two DSPs, memory, and ARM.

Published in:

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International  (Volume:1 )

Date of Conference:

7-7 Feb. 2002