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A diagonal-interconnect architecture and its application to RISC core design

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7 Author(s)
Igarashi, M. ; Toshiba Corp., Tokyo, Japan ; Mitsuhashi, T. ; Le, A. ; Kazi, S.
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Applying a design methodology based on an interconnect architecture characterized by pervasive use of diagonal wiring to a 128 b RISC processor core design results in 19.8 % path delay reduction and 10 % area reduction, compared to the conventional orthogonal interconnect architecture.

Published in:

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International  (Volume:1 )

Date of Conference:

7-7 Feb. 2002