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A 1.6 Gsample/s 6b flash analog-to-digital converter in 0.18 /spl mu/m CMOS is for storage read channels. The array of amplifiers and averaging resistors is terminated with less overrange while maintaining full-scale linearity. Consuming 340 mW, it achieves 5.7 effective bits at DC and 5 effective bits at 660 MHz.
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International (Volume:1 )
Date of Conference: 7-7 Feb. 2002