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Combining a negative-gate channel-erasing NOR flash memory technology with an aggressively-scaled NAND flash process technology results in a 64 Mb NOR flash memory with 0.27 /spl mu/m/sup 2/ cell and 44 mm/sup 2/ chip. The flash memory provides 4 independent banks for flexible dual operation and unique block redundancy for yield.
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International (Volume:1 )
Date of Conference: 7-7 Feb. 2002