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Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

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3 Author(s)
Borse, D.G. ; Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai, India ; Vaidya, S.J. ; Chandorkar, A.N.

Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N2O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied

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Electron Devices, IEEE Transactions on  (Volume:49 ,  Issue: 4 )