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Technology and reliability constrained future copper interconnects. II. Performance implications

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4 Author(s)
Kapur, Pawan ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Chandra, G. ; McVittie, James P. ; Saraswat, K.C.

For pt. I see ibid., vol.49, no.4, pp.590-7 (2002). This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity

Published in:

Electron Devices, IEEE Transactions on  (Volume:49 ,  Issue: 4 )

Date of Publication:

Apr 2002

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