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A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

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3 Author(s)
Hafed, M.M. ; Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada ; Abaskharoun, N. ; Roberts, G.W.

An area-efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). Several prototypes were fabricated in a triple-metal 3.3-V 0.35-μm CMOS process, and were demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks at a clock rate of 20 MHz (limited by our experimental setup). Designed for 8 bits of quantization, a spurious-free dynamic range (SFDR) of 65 dB at 500 KHz and 61 dB at Nyquist (20.001 MHz) was demonstrated using our prototypes. High-frequency narrow-band signals (extending into the gigahertz range) have been captured through subsampling and the use of a high-bandwidth front-end sampling network. Similarly, circuit phenomena that are broadband in nature were measured by using a delayed-clock subsampling mechanism in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. Delaying the clock is performed using a voltage-controlled delay line tuned by a self-biased delay-locked loop, which allowed for a timing resolution of about one gate delay (~200 ps). The proposed test core occupies an area equivalent to only about 7000 standard-cell 2-input NAND gates

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:37 ,  Issue: 4 )