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I/sub DDQ/ testing for deep-submicron ICs: challenges and solutions

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4 Author(s)
Zhanping Chen ; Intel, Hillsboro, OR, USA ; Liqiong Wei ; A. Keshavarzi ; K. Roy

The use of low-threshold devices in scaled low-voltage CMOS circuits leads to increased intrinsic leakage current. As a result, I/sub DDQ/ testing requires different techniques to remain effective.

Published in:

IEEE Design & Test of Computers  (Volume:19 ,  Issue: 2 )