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Test generation for multiple-threshold gate-delay fault model

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5 Author(s)
Nakao, M. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Kiyoshige, Y. ; Hatayama, K. ; Sato, Y.
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Presents a practical coverage metric in delay testing, which is called a multiple-threshold gate-delay fault model, to obtain high quality tests for large circuits. Fault efficiencies for given multiple thresholds of the delay fault size are computed, and their entirety describes the quality of tests. The approach guarantees that each gate-delay fault is not only robustly tested on almost the longest path, but also tested under the condition as a transition fault, by using two-pattern tests with a pattern-independent timing. We present procedures of path selection, fault simulation and test generation, where the path-status graph technique is used for an efficient computation. Experimental results for industrial circuits demonstrate that the proposed method can achieve high fault efficiencies for gate-delay faults having various fault sizes in a practical processing time

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Test Symposium, 2001. Proceedings. 10th Asian

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