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Logic synthesis for ASICs

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2 Author(s)
R. Damiano ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; D. S. Reeves

The steps performed by logic synthesis software, which transforms a specification of a function and its timing into an application-specific integrated circuit (ASIC) such as a gate or standard cell array, programmable logic device (PLD), or field programmable gate array (FPGA), are outlined. Hardware description languages, foundry pacts, and testability are discussed. A table describing representative software packages is given.<>

Published in:

IEEE Spectrum  (Volume:28 ,  Issue: 11 )