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A silicon bipolar decision circuit operating up to 15 Gb/s

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4 Author(s)
J. Hauenschild ; Ruhr-Univ., Bochum, Germany ; H. -M. Rein ; W. McFarland ; D. Pettengill

A master-slave D-flip-flop (MS-D-FF) IC usable as a decision circuit has been realized in an advanced self-aligned silicon bipolar technology using 0.8-μm lithography. The circuit has been operated up to 15 Gb/s (at a clock phase margin (CPM) of 180°C) with a 5-V supply voltage. The data rate of 15 Gb/s is not the limit of this decision circuit if CPM values lower than 180° can be tolerated, or if input voltage swings above 400 mVp-p are available

Published in:

IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 11 )